1. Field of the Invention
The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic apparatus including the solid-state imaging device.
2. Description of the Related Art
CMOS solid-state imaging devices include a plurality of pixels arranged in a desired pattern, the pixels each including a photodiode and a plurality of MOS transistors. The photodiode serves as a photoelectric transducer which generates signal charge according to a quantity of received light and stores the charge, and the plurality of MOS transistors serve as elements for transferring signal charge from the photodiode. In each of the pixels, signal charge is obtained by illuminating light and output as a pixel signal. The output pixel signal is processed by a predetermined signal processing circuit and output as a video signal to the outside.
In order to improve the characteristics of solid-state imaging devices, attempts have recently been made to reduce a pixel size and improve a quantity (Qs) of saturation electric charge and sensitivity. Japanese Unexamined Patent Application Publication No. 2005-223084 discloses a solid-state imaging device using a transfer transistor having a vertical gate electrode which is formed in the depth direction of a semiconductor substrate in order to permit miniaturization of a pixel size without decreasing a quantity (Qs) of saturation electric charge and sensitivity.
FIG. 33 shows a schematic sectional configuration of a related-art solid-state imaging device described in Japanese Unexamined Patent Application Publication No. 2005-223084.
As shown in FIG. 33, a solid-state imaging device 100 of this publication includes a p-type semiconductor substrate 101, a photodiode 104 formed in the semiconductor substrate 101 and constituting each pixel, and a transfer transistor Tra.
The photodiode 104 includes a p-type high-concentration impurity region (p+ region) 105 formed on the surface side of the semiconductor substrate 101, an n-type high-concentration impurity region (n+ region) 103 formed in contact with the p+ region 105, and an n-type low-concentration impurity region (n− region) 102. A main pn junction constituting the photodiode 104 is formed by a junction between the p+ region 105 and the n+ region 103.
The transfer transistor Tra is an n-channel MOS transistor for transferring signal charge stored in the photodiode 104. The transfer transistor Tra includes a floating diffusion portion 107 provided on the surface side of the semiconductor substrate 101 and a vertical gate electrode 108 formed from the surface side of the semiconductor substrate 101 in the depth direction through a gate insulating film 106. The vertical gate electrode 108 is in contact with the floating diffusion portion 107 with the gate insulating film 106 provided therebetween, and is formed to a position deeper than the pn junction of the photodiode 104. The vertical gate electrode 108 is formed by forming the gate insulating film 106 in a trench which is formed from the surface side of the semiconductor substrate 101 to a depth reaching the pn junction of the photodiode 104 and then filling a portion above the gate insulating film 106 in the trench.
In the transfer transistor Tra, a transfer channel is formed from the pn junction constituting the photodiode 104 to the floating diffusion portion 107 along the vertical gate electrode 108 in the depth direction of the semiconductor substrate 101.
In the solid-state imaging device 100 having the above-described configuration, light incident on the back side of the semiconductor substrate 101 is photoelectrically converted by the photodiode 104 to store signal charge in the photodiode 104. When a positive voltage is applied to the vertical gate electrode 108 of the transfer transistor Tra, the signal charge stored in the photodiode 104 is read out to the floating diffusion portion 107 through transfer paths shown by broken lines a in FIG. 33.
In the above-described configuration, the photodiode 104 is formed in the depth direction of the semiconductor substrate 101, and the signal charge stored in the photodiode 104 is read out by the vertical gate electrode 108. Therefore, miniaturization of the pixels does not decrease the quantity (Qs) of saturation electric charge and sensitivity of the photodiode 104. In addition, a backside illumination type, a MOS transistor and a wiring layer are not formed on the illumination side, thereby increasing an opening area.
However, when the signal charge stored in the photodiode 104 which is buried in the semiconductor substrate 101 is read out from the inside of the semiconductor substrate 101 to the surface side thereof by the vertical gate electrode 108, the charge transfer path is very long as shown by the broken lines a. Therefore, complete transfer of signal charges is difficult as compared with a plane-type gate electrode used in usual solid-state imaging devices.